The recent convergence of technologies, big data analytics and cloud computing brings opportunities to develop new platforms and products for the semiconductor chip design industry.
Started in 2009 and headquartered in Singapore, Plunify is an early mover in combining Machine Learning and semiconductor chip design knowledge to solve FPGA timing / fitting problems. We provide an expert software called InTime which electronics makers use in order to accelerate product Time-To-Market and lower product costs.
We are looking for a new team member with excellent FPGA and CAD scripting skills; or someone who cannot sleep at night if an FPGA design has timing / fitting problems.
His/her time will be spent like this:
• (40%) Hands-on FPGA timing closure and optimization (Area/Power as well). This involves learning about our unique Machine Learning approach as well.
• (60%) Automating CAD flows to implement features in our software.
Requirements:
• Proficient in scripting languages like Tcl/Perl, and in using command-line APIs.
• Experience in automating FPGA workflows, for example, knowing why, when and how to go from synthesis to place-and-route and then timing analysis.
• Working knowledge of Xilinx (ISE, Vivado) and/or Altera (Quartus) FPGA design tools and flows.
• Familiarity with software engineering best practices.
Job Type
Salary
Status
Closing Date
